The present invention relates to impedance matching in DDR memory, and more specifically, to adjusting resistances between a driver and memory modules.
The design of a computing system is limited by the number of dual in-line memory modules (DIMM) that can be addressed on a single bus. Reflections increase as additional DIMMs are placed on a bus which shrinks the size of the useful data eye required for the receiving DIMM to process the signals. Current double data rate (DDR) registered DIMMs are limited in speed due to this configuration.